Errors massedly generated in the form of burst during data transmission by a transmission system or reading of data on an optical recording medium have been known as a burst error. For example, data is recorded at a high density within a limited space of a recording medium in the optical recording medium, so that even a small flow would result in a number of defect bits.
In general, as an error correcting code for correcting an error, there has been widely used BCH code (Bose-Chaudhuri-Hocquenghem code) including Reed-Solomon Code.
Even when the error lasts too long to be correctable by such as error correcting code, an interleaving method may be used. According to this method, recorded data or transmission data is broken up according to a certain rule, so that when the data is restored, the burst error is dispersed into various portions and errors in the respective portions are correctable by the error correcting code.
FIG. 9 illustrates a block diagram of a conventional interleaving apparatus. For convenience, 3.times.4 interleaving for each 12 data is illustrated for an example. A basic method for interleaving is such that: when data from a data source 50 is transmitted or recorded on a recording medium, data output from the data source 50 is sequentially written once into a read/write memory (RAM) 48 and the data is read in an address sequence different from an address sequence when the data is written, to interleave the data.
In the conventional apparatus of FIG. 9, a counter 40 is used for generating an address and read-only-memories (ROM) 42 and 46 are used for changing the output data from the counter between reading and writing. Numerals shown in FIGS. 10A and 10B, for example, are written in ROMs 42 and 46.
A brief description of an operation of the conventional apparatus will be now given.
If data A, B, C, D, E, F . . . is output from the data source 50 as illustrated in an upper row of FIG. 11, the data is once written in RAM 48. In the writing, a reading/writing switching signal R/W (hereinafter referred to simply as signal RW) becomes "low" and ROM 46 is inabled, while ROM 42 is disabled through an inverter 44.
Since data same as the addresses of ROM 46 are written in ROM 46 (in this case, ROM 46 functions just as a buffer), the addreses of RAM 48 are addressed in an ascending order if the counter 40 is an up-counter and written in as illustrated in FIG. 10C.
When RAM 48 is read, RW signal becomes "high" and ROM is enabled, while ROM 46 is desabled. Therefore, the output data from the counter 40 is translated by ROM 42. More particularly, the addresses of RAM 48 are addressed in order of 0, 4, 8, 1, 5. . . as illustrated in FIG. 10A. As a result of this, the data is read from RAM 48 in a sequence different from the writing sequence as illustrated in a lower row of FIG. 11.
The processing operation as described above is equivalent to an operation reading, sequentially in a column direction, a matrix of 3.times.4 of FIG. 12, in which serial data is sequentially arranged in a row direction.
A receiving unit for transmitted data or a reproducing unit for a recording medium comprises an apparatus as shown in FIG. 9 which restors the serial data into an original order by carrying our a procedure reverse to the write/read procedure as described above. More particularly, the data is once written in RAM 48 according to the output from ROM 42 and it is thereafter read according to the output from ROM 46.
Since ROMs are used in the conventional apparatus as described above, a considerably large number of gates are needed. This is a problem to form the circuit of the apparatus in LSI. Further, since address signals from the counter for addressing a storing means are translated by ROM, an accessing time of RAM is substantially increased, preventing speed-up of an interleaving operation.